High-bandwidth Address Generation Unit

Carlo Galuzzi; Chunyang Gou; Humberto Calderon; Georgi N. Gaydadjiev; Stamatis Vassiliadis

doi:10.1007/s11265-008-0174-x

High-bandwidth Address Generation Unit

Carlo Galuzzi^*, Chunyang Gou, Humberto Calderon, Georgi N. Gaydadjiev, Stamatis Vassiliadis

^*Corresponding author for this work

Research output: Contribution to journal › Article › Academic › peer-review

4 Citations (Scopus)

43 Downloads (Pure)

Abstract

In this paper we present an efficient data fetch circuitry to retrieve several operands from a n-way parallel memory system in a single machine cycle. The proposed address generation unit operates with an improved version of the low-order parallel memory access approach. Our design supports data structures of arbitrary lengths and different odd strides. The experimental results show that our address generation unit is capable of generating eight 32 -aEuro parts per thousand bit addresses every 6 ns for different strides when implemented on a VIRTEX-II PRO xc2vp30-7ff1696 FPGA device using only trivial hardware resources.

Original language	English
Pages (from-to)	33-44
Number of pages	12
Journal	Journal of vlsi signal processing systems for signal image and video technology
Volume	57
Issue number	1
DOIs	https://doi.org/10.1007/s11265-008-0174-x
Publication status	Published - Oct-2009
Externally published	Yes
Event	7th SAMOS International Workshop - Samos, Greece Duration: 16-Jul-2007 → 19-Jul-2007

Keywords

Address generation unit
Parallel memory
Stride
MEMORY SYSTEM
VECTOR
ACCESS
COMPUTER

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10.1007/s11265-008-0174-xLicence: CC BY-NC

High-bandwidth Address Generation UnitFinal publisher's version, 578 KBLicence: CC BY-NC

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@article{815caddfa3944bf68efd99d2bc3b92e9,

title = "High-bandwidth Address Generation Unit",

abstract = "In this paper we present an efficient data fetch circuitry to retrieve several operands from a n-way parallel memory system in a single machine cycle. The proposed address generation unit operates with an improved version of the low-order parallel memory access approach. Our design supports data structures of arbitrary lengths and different odd strides. The experimental results show that our address generation unit is capable of generating eight 32 -aEuro parts per thousand bit addresses every 6 ns for different strides when implemented on a VIRTEX-II PRO xc2vp30-7ff1696 FPGA device using only trivial hardware resources.",

keywords = "Address generation unit, Parallel memory, Stride, MEMORY SYSTEM, VECTOR, ACCESS, COMPUTER",

author = "Carlo Galuzzi and Chunyang Gou and Humberto Calderon and Gaydadjiev, {Georgi N.} and Stamatis Vassiliadis",

year = "2009",

month = oct,

doi = "10.1007/s11265-008-0174-x",

language = "English",

volume = "57",

pages = "33--44",

journal = "Journal of vlsi signal processing systems for signal image and video technology",

issn = "1939-8018",

publisher = "Springer",

number = "1",

note = "7th SAMOS International Workshop ; Conference date: 16-07-2007 Through 19-07-2007",

}

TY - JOUR

T1 - High-bandwidth Address Generation Unit

AU - Galuzzi, Carlo

AU - Gou, Chunyang

AU - Calderon, Humberto

AU - Gaydadjiev, Georgi N.

AU - Vassiliadis, Stamatis

PY - 2009/10

Y1 - 2009/10

N2 - In this paper we present an efficient data fetch circuitry to retrieve several operands from a n-way parallel memory system in a single machine cycle. The proposed address generation unit operates with an improved version of the low-order parallel memory access approach. Our design supports data structures of arbitrary lengths and different odd strides. The experimental results show that our address generation unit is capable of generating eight 32 -aEuro parts per thousand bit addresses every 6 ns for different strides when implemented on a VIRTEX-II PRO xc2vp30-7ff1696 FPGA device using only trivial hardware resources.

AB - In this paper we present an efficient data fetch circuitry to retrieve several operands from a n-way parallel memory system in a single machine cycle. The proposed address generation unit operates with an improved version of the low-order parallel memory access approach. Our design supports data structures of arbitrary lengths and different odd strides. The experimental results show that our address generation unit is capable of generating eight 32 -aEuro parts per thousand bit addresses every 6 ns for different strides when implemented on a VIRTEX-II PRO xc2vp30-7ff1696 FPGA device using only trivial hardware resources.

KW - Address generation unit

KW - Parallel memory

KW - Stride

KW - MEMORY SYSTEM

KW - VECTOR

KW - ACCESS

KW - COMPUTER

U2 - 10.1007/s11265-008-0174-x

DO - 10.1007/s11265-008-0174-x

M3 - Article

SN - 1939-8018

VL - 57

SP - 33

EP - 44

JO - Journal of vlsi signal processing systems for signal image and video technology

JF - Journal of vlsi signal processing systems for signal image and video technology

IS - 1

T2 - 7th SAMOS International Workshop

Y2 - 16 July 2007 through 19 July 2007

ER -

High-bandwidth Address Generation Unit

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